Code name
This parameter characterizes, firstly, the technical process (see above), and secondly, some features of the internal structure of processors. A new (or at least updated) codename is introduced to the market with each new CPU generation; chips of the same architecture are "coevals", but may belong to different series (see above). At the same time, one generation can include both one and several code names.
Here are the most common Intel codenames today:
Cascade Lake-X (10th gen),
Comet Lake (10th gen),
Comet Lake Refresh (10th generation),
Rocket Lake (11th generation),
Alder Lake (12th generation),
Raptor Lake (13th generation),
Raptor Lake Refresh (14th generation).
For AMD, this list includes
Zen+ Picasso,
Zen2 Matisse,
Zen2 Renoir,
Zen3 Vermeer,
Zen3 Cezanne,
Zen4 Raphael and
Zen4 Phoenix.
Multithreading
Processor support for Hyper-threading.
Hyper-threading is actually a variant of simultaneous multithreading (SMT) developed by Intel and used in its chips since 2002. This technology is used to optimize the load on each physical processor core. Its key principle (simplified) is that each such core is defined by the system as 2 logical cores — for example, the system “sees” a dual-core processor as a quad-core one. At the same time, each physical core constantly switches between two logical cores, in fact, between two threads of commands: when a delay occurs in one thread (for example, in case of an error or while waiting for the result of the previous instruction), the core does not idle, but starts executing the second thread commands. Thanks to this technology, the response time of the processor is reduced, and in server systems, stability is increased with numerous connected users.
In AMD processors, a similar function is used under the original name SMT (see below).
Performance-core Base
The base clock speed of high-performance P-cores for Intel processors on a hybrid architecture.
Performance-core Max
Maximum Turbo clock speed for Performance Cores from the Intel Hybrid Processor League.
L1 cache
The amount of Level 1 (L1) cache provided by the processor.
Cache is an intermediate memory buffer into which the most frequently used data from RAM is written when the processor is running. This speeds up access to them and has a positive effect on system performance. The larger the cache, the more data can be stored in it for quick access and the higher the performance. Level 1 cache has the highest performance and the smallest volume — up to 128 KB. It is an integral part of any processor.
L2 cache
The amount of Level 2 (L2) cache provided by the processor.
Cache is an intermediate memory buffer into which the most frequently used data from RAM is written during processor operation. This speeds up access to them and has a positive effect on system performance. The larger the cache, the more data can be stored in it for quick access and the higher the performance. Level 2 cache volume can reach 12 MB, the vast majority of modern processors have such a cache.
TDP
The amount of heat generated by the processor during normal operation. This parameter determines the requirements for the cooling system necessary for the normal operation of the processor, therefore it is sometimes called TDP — thermal design power, literally “thermal (cooling) system power”. Simply put, if the processor has a heat dissipation of 60 W, it needs a cooling system that can remove at least this amount of heat. Accordingly, the lower the TDP, the lower the requirements for the cooling system.
Low TDP values(up to 50 W) are especially critical for PCs that do not have the ability to install powerful cooling systems — in particular, systems in compact cases where a powerful cooler simply does not fit.
Passmark CPU Mark
The result shown by the processor in the Passmark CPU Mark test.
Passmark CPU Mark is a comprehensive test that checks not only the gaming capabilities of the CPU, but also its performance in other modes, based on which it displays the overall score; this score can be used to fairly reliably evaluate the processor as a whole.
