Comparison Crucial Ballistix Tactical DDR4 2x4GB BLT2C4G4D26AFTA vs HyperX Fury DDR4 2x4GB HX426C15FBK2/8
Add to comparison |  |  |
|---|---|---|
| Crucial Ballistix Tactical DDR4 2x4GB BLT2C4G4D26AFTA | HyperX Fury DDR4 2x4GB HX426C15FBK2/8 | |
from $72.00 | from $127.22 | |
| TOP sellers | ||
| Memory capacity | 2 x 4GB | 2 x 4GB |
| Form factor | DIMM (PC) | DIMM (PC) |
| Type | DDR4 | DDR4 |
| Memory rank | single rank | |
Specs | ||
| Speed | 2666 MT/s | 2666 MT/s |
| Clock speed | 21300 MB/s | 21300 MB/s |
| Timing diagram | 16-16-16 | 15-17-17 |
| First Word Latency | 12 ns | 11.25 ns |
| Voltage | 1.2 В | 1.2 В |
| Cooling | radiator | radiator |
| Strip profile | standard 35.6 mm | standard 34 mm |
| More features | XMP | XMP |
| Added to E-Catalog | april 2016 | october 2015 |
Compare Crucial BLT2C4G4D26AFTA and HyperX HX426C15FBK2/8 Crucial Ballistix Tactical DDR4 2x4GB и HyperX Fury DDR4 2x4GB?
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Glossary
Memory rank
The number of ranks provided in the memory bar.
The rank in this case is called one logical module — a chipset with a total capacity of 64 bits. If there is more than one rank, this means that several logical ones are implemented on one physical module, and they use the data transmission channel alternately. A similar design is used in order to achieve large amounts of RAM with a limited number of slots for individual brackets. At the same time, it should be said that for consumer computers, you can not pay much attention to the memory rank — more precisely, peer-to-peer modules are quite enough for them. But for servers and powerful workstations, two-, four- and even eight-rank solutions are produced.
Note that other things being equal, a larger number of ranks allows achieving larger volumes, however, it requires more computing power and increases the load on the system.
The rank in this case is called one logical module — a chipset with a total capacity of 64 bits. If there is more than one rank, this means that several logical ones are implemented on one physical module, and they use the data transmission channel alternately. A similar design is used in order to achieve large amounts of RAM with a limited number of slots for individual brackets. At the same time, it should be said that for consumer computers, you can not pay much attention to the memory rank — more precisely, peer-to-peer modules are quite enough for them. But for servers and powerful workstations, two-, four- and even eight-rank solutions are produced.
Note that other things being equal, a larger number of ranks allows achieving larger volumes, however, it requires more computing power and increases the load on the system.
Timing diagram
Timing is a term that refers to the time it takes to complete an operation. To understand the timing scheme, you need to know that structurally RAM consists of banks (from 2 to 8 per module), each of which, in turn, has rows and columns, like a table; when accessing memory, the bank is selected first, then the row, then the column. The timing scheme shows the time during which the four main operations are performed when working with RAM, and is usually written in four digits in the format CL-Trcd-Trp-Tras, where
CL is the minimum delay between receiving a command to read data and the start of their transfer;
Trcd — the minimum time between the selection of a row and the selection of a column in it;
Trp is the minimum time to close a row, that is, the delay between the signal and the actual closing. Only one bank line can be opened at a time; Before opening the next line, you must close the previous one.
Tras — the minimum time the row is active, in other words, the shortest time after which the row can be commanded to close after it has been opened.
Time in the timing scheme is measured in cycles, so the actual memory performance depends not only on the timing scheme, but also on the clock frequency. For example, 1600 MHz 8-8-8-24 memory will run at the same speed as 800 MHz 4-4-4-12 memory—in either case timings, if expressed in nanoseconds, will be 5-5-5-15.
CL is the minimum delay between receiving a command to read data and the start of their transfer;
Trcd — the minimum time between the selection of a row and the selection of a column in it;
Trp is the minimum time to close a row, that is, the delay between the signal and the actual closing. Only one bank line can be opened at a time; Before opening the next line, you must close the previous one.
Tras — the minimum time the row is active, in other words, the shortest time after which the row can be commanded to close after it has been opened.
Time in the timing scheme is measured in cycles, so the actual memory performance depends not only on the timing scheme, but also on the clock frequency. For example, 1600 MHz 8-8-8-24 memory will run at the same speed as 800 MHz 4-4-4-12 memory—in either case timings, if expressed in nanoseconds, will be 5-5-5-15.
First Word Latency
First Word Latency shows how long it takes for RAM to start delivering the first block of data after a request. The lower this value, the faster the memory responds, which is particularly interesting in gaming systems and high-performance PCs, where responsiveness and minimal delays are important.
For memory, this is a more illustrative indicator of latency than just CAS Latency, because it takes into account not only the timings but also the operating frequency. This is why two sets of RAM with different CL values can actually have a very similar response speed: for example, DDR4-3200 CL16 and DDR5-6000 CL30 both deliver approximately 10 ns of First Word Latency.
For memory, this is a more illustrative indicator of latency than just CAS Latency, because it takes into account not only the timings but also the operating frequency. This is why two sets of RAM with different CL values can actually have a very similar response speed: for example, DDR4-3200 CL16 and DDR5-6000 CL30 both deliver approximately 10 ns of First Word Latency.